Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TSV to at least one of a test input and a test evaluation circuit.
Legal claims defining the scope of protection, as filed with the USPTO.
4. The apparatus of claim 1, wherein the chain of TSVs comprise a vertical series of TSVs.
5. The apparatus of claim 1, wherein the plurality of (IC) devices are homogeneous devices.
6. The apparatus of claim 1, wherein the plurality of (IC) devices are heterogeneous devices.
7. The apparatus of claim 1, wherein the plurality of (IC) devices are volatile memory devices.
8. The apparatus of claim 1, wherein the plurality of (IC) devices are non-volatile memory devices.
9. The apparatus of claim 1, further comprising a field of TSVs, wherein the field of TSVs comprises a plurality of the chain of TSVs.
10. The apparatus of claim 9, wherein the field of TSVs comprises a single two-dimensional array of TSVs in a single IC device.
11. The apparatus of claim 9, wherein the field of TSVs comprises multiple arrays of TSVs in a three-dimensional stack of the IC devices.
13. The method of claim 12, further comprising coupling the TSVs to an input node via a first switch.
14. The method of claim 12, further comprising coupling the TSVs to a test node via a second switch and an output driver.
15. The method of claim 12, wherein the plurality of (IC) devices are homogeneous devices.
16. The method of claim 12, wherein the plurality of (IC) devices are volatile memory devices.
19. The apparatus of claim 18, wherein the field of TSVs comprises a single two-dimensional array of TSVs in a single IC device.
20. The apparatus of claim 18, wherein the field of TSVs comprises multiple arrays of TSVs in a three-dimensional stack of integrated circuit IC devices.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 9, 2021
March 7, 2023
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