A method of manufacture for a semiconductor package includes; forming a molding member on side surfaces of the semiconductor chips, using an adhesive to attach a carrier substrate to upper surfaces of the molding member and the semiconductor chips, using a first blade having a first blade-width to cut away selected portions of the carrier substrate and portions of the adhesive underlying the selected portions of the carrier substrate, and using the first blade to partially cut into an upper surface of the molding member to form a first cutting groove, wherein the selected portions of the carrier substrate are dispose above portions of the molding member between adjacent ones of semiconductor chips, using a second blade having a second blade-width narrower than the first blade-width to cut through a lower surface of the molding member to form a second cutting groove, wherein a combination of the first cutting groove and the second cutting groove separate a package structure including a semiconductor chip supported by a cut portion of the carrier substrate and bonding the package structure to an upper surface of a package substrate.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The semiconductor package of claim 1, wherein a vertical height of the protruding sidewall is equal to a sum of the first distance, the second distance and a vertical height of the outer side surface.
3. The semiconductor package of claim 2, wherein the vertical height of the protruding sidewall ranges between about 800 μm to about 900 μm, the first distance is at least about 20 μm and the second distance is at least about 20 μm.
4. The semiconductor package of claim 1, wherein the molding member completely surrounds a combination of the first semiconductor chip and the stacked plurality of second semiconductor chips and is interposed between the first semiconductor chip and the stacked plurality of second semiconductor chips.
5. The semiconductor package of claim 1, wherein the first semiconductor chip is a central processing unit or a graphic processing unit, and each second semiconductor chip is a high-bandwidth memory chip.
6. The semiconductor package of claim 1, wherein the upper end of the protruding sidewall extends horizontally from a side surface of the stacked plurality of second semiconductor chips by a first width, and the lower end of the protruding sidewall extends horizontally from the side surface of the stacked plurality of second semiconductor chips by a second width less than the first width.
7. The semiconductor package of claim 1, wherein the molding member includes an epoxy molding compound.
8. The semiconductor package of claim 1, wherein the interposer includes connection vias electrically connecting the first semiconductor chip and the stacked plurality of second semiconductor chips with at least one conductive pattern on the upper surface of the package substrate.
12. The semiconductor package of claim 11, wherein the lower portion of the molding member has a horizontally extending width greater than the horizontally extending width of the upper portion of the molding member and less than the horizontally extending width of the protruding sidewall.
13. The semiconductor package of claim 11, wherein the interposer includes connection vias electrically connecting the semiconductor chip with a conductive pattern on the upper surface of the package substrate.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 17, 2021
March 21, 2023
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