A semiconductor structure includes a first transistor comprising a first gate structure over a first active region in a substrate. The semiconductor structure further includes a second active region in the substrate. The semiconductor structure further includes a first butted contact. The butted contact includes a first portion extending in a first direction and overlapping the second active region, and a second portion extending from the first portion in a second direction, different from the first direction, wherein the second portion directly contacts the first gate structure.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The semiconductor structure of claim 1, further comprising a second transistor, wherein the second transistor comprises a second gate structure over the second active region.
3. The semiconductor structure of claim 2, further comprising a second butted contact electrically connecting the second gate structure to the first active region.
4. The semiconductor structure of claim 3, wherein the second butted contact directly contacts the second gate structure.
6. The semiconductor structure of claim 5, wherein the third direction is parallel to the second direction.
7. The semiconductor structure of claim 2, further comprising a contact electrically connected to the second active region on an opposite side of the second gate structure from the first butted contact.
8. The semiconductor structure of claim 1, wherein a width of the first butted contact increases as a distance from the substrate increases.
9. The semiconductor structure of claim 1, further comprising an isolation region in the substrate, wherein the first gate structure at least partially overlaps the isolation region.
11. The method of claim 10, wherein etching the dielectric layer further comprises removing a portion of a sidewall spacer from the first gate electrode.
12. The method of claim 11, wherein removing the portion of the sidewall spacer comprises exposing a sidewall of the first gate electrode, and depositing the conductive material comprises depositing the conductive material along the exposed sidewall of the first gate electrode.
13. The method of claim 10, further comprising forming a source/drain feature in the second active region, wherein etching the dielectric layer comprises exposing the source/drain feature.
14. The method of claim 10, wherein forming the first gate electrode comprises forming the gate electrode at least partially overlapping an isolation structure.
16. The method of claim 15, wherein electrically connecting the voltage to the second gate structure comprises electrically connecting the voltage to the second gate structure using an L-shaped butted contact.
17. The method of claim 15, wherein supplying the voltage comprises supplying a power supply voltage.
18. The method of claim 15, wherein supplying the voltage comprises supplying a ground voltage.
19. The method of claim 15, wherein electrically connecting the voltage to the second gate structure comprises making a channel of a second transistor including the second gate structure conductive.
20. The method of claim 15, wherein electrically connecting the voltage to the second gate structure comprises making a channel of a second transistor including the second gate structure non-conductive.
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December 3, 2020
March 21, 2023
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