The present disclosure relates to semiconductor structures and, more particularly, to floating-gate devices and methods of manufacture. The structure includes: a gate structure comprising a gate dielectric material and a gate electrode; and a vertically stacked capacitor over and in electrical connection to the gate electrode.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The structure of claim 1, wherein the vertically stacked capacitor over the gate electrode includes multiple wiring layers each of which comprises multiple wirings separated by dielectric material on a same wiring level.
3. The structure of claim 2, wherein the vertically stacked capacitor is electrically connected to the gate electrode by interconnects and the multiple wiring layers are spaced apart from one another on the same wiring layer by the dielectric material and separated by an insulator material between wiring layers of the multiple wiring layers.
4. The structure of claim 2, wherein the gate dielectric material has a thickness of from 200 Å and greater, and a ratio of the thickness of the gate dielectric material to a thickness of back end of line dielectric material is 1:1 to 1:4.
5. The structure of claim 2, wherein the vertically stacked capacitor has a same footprint as the gate structure and the multiple wirings are configured as fingers.
6. The structure of claim 2, wherein the vertically stacked capacitor has a footprint smaller than the gate structure.
7. The structure of claim 2, wherein the gate structure is a floating gate device.
8. The structure of claim 7, wherein the vertically stacked capacitor includes both a floating gate voltage (fg) and a control gate voltage applied through the vertically stacked capacitor.
9. The structure of claim 8, wherein the vertically stacked capacitor provides capacitive coupling controlled through various wirings of the vertically stacked capacitor, which induces charge transfer from the gate structure to a either substrate or terminals contacting the gate electrode.
10. The structure of claim 2, wherein the vertically stacked capacitor is a metal-oxide-metal (MOM) capacitor.
11. The structure of claim 2, wherein the vertically stacked capacitor is an alternate polarity metal-oxide-metal (APMOM) capacitor comprising wiring on a same wiring level alternating between positive and negative.
13. The structure of claim 12, wherein the vertically stacked capacitor includes multiple vertically stacked wiring layers separated by a nitride material, and each of the multiple vertically stacked wiring layers includes the multiple wirings comprising the multiple fingers separated from one another by the interlevel dielectric material.
14. The structure of claim 12, wherein the gate dielectric material has a thickness of from 200 Å and greater, and a ratio of the thickness of the gate dielectric material to a thickness of back end of line dielectric material is 1:1 to 1:4.
15. The structure of claim 12, wherein the vertically stacked capacitor includes both a floating gate voltage (fg) and a control gate voltage applied through the vertically stacked capacitor and the multiple wirings of the vertically stacked capacitor comprise multiple wiring fingers.
16. The structure of claim 12, wherein the vertically stacked capacitor provides capacitive coupling controlled through various wirings of the vertically stacked capacitor, which induces charge transfer from the gate structure to a either substrate or terminals contacting the gate electrode.
17. The structure of claim 12, wherein the vertically stacked capacitor is a metal-oxide-metal (MOM) capacitor.
18. The structure of claim 12, wherein the vertically stacked capacitor is an alternate polarity metal-oxide-metal (APMOM) capacitor comprising wiring on a same wiring level alternating between positive and negative.
20. The structure of claim 12, wherein the vertically stacked capacitor comprises the multiple wirings on multiple wiring layers, each of the multiple wirings comprise multiple fingers separated by the interlevel dielectric material on a same wiring layer and on different wring layers, and each of the multiple wirings is confined within the edges of the floating gate structure and has one of a same and smaller footprint than the floating gate structure.
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June 10, 2020
March 21, 2023
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