Systems, circuitry and methods measure data transition metrics of incoming data, average the measurements of each metric at a set time interval for multiple intervals to generate multiple averaged values, and select a maximum of the multiple averaged values for each metric. The maximum values of each measurement cycle are compared with corresponding multiple thresholds defining respective ranges, and the outputs are used by a state machine to determine an equalization level and the rate of the incoming data. When the thresholds are not met, the state machine adjusts the equalization level, and when a sub-rate is detected using a third threshold for one of the metrics, the clock rate is also adjusted. Locking of a clock and data recovery (CDR) circuit is attempted when the maximum values for each metric are within their respective ranges.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The data transition tracking circuitry of claim 1, wherein the comparator circuitry includes a first comparator having a first maximum signal input and a first threshold input, and a second comparator having a second maximum signal input and a second threshold input.
4. The data transition tracking circuitry of claim 2, wherein the first comparator is configured to determine whether the maximum signal is greater than the first threshold, and the second comparator is configured to determine whether the maximum signal is greater than the second threshold.
7. The data transition tracking circuitry of claim 6, wherein the data transition measurement circuitry includes logic circuitry configured to receive deserialized data derived from the sequence of data units.
8. The data transition tracking circuitry of claim 7, wherein the data transition measurement circuitry further includes a summer circuit coupled to the logic circuitry, and an integrator circuit coupled to the logic circuitry.
9. The data transition tracking circuitry of claim 8, wherein the integrator circuit is coupled to the averaging circuit.
13. The system of claim 11, wherein the DTD circuitry includes DTD logic having first and second inputs coupled to first and second outputs of the first and second DTD comparators respectively, the logic having an output at which signal indicative of whether a corresponding one of the maximum DTD values is within a set range is output.
14. The system of claim 11, wherein the SBT circuitry includes SBT logic having first and second inputs coupled to first and second outputs of the first and second SBT comparators respectively, the logic having an output at which a signal indicative of whether a corresponding one of the maximum SBT values is within a set range is output.
15. The system of claim 11, wherein the SBT circuitry includes a third SBT comparator having a maximum SBT value input to receive each maximum SBT value and a third SBT threshold input.
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January 11, 2022
April 4, 2023
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