In various embodiments, a bonded structure is disclosed. The bonded structure can include an element and a passive electronic component having a first surface bonded to the element and a second surface opposite the first surface. The passive electronic component can comprise a first anode terminal bonded to a corresponding second anode terminal of the element and a first cathode terminal bonded to a corresponding second cathode terminal of the element. The first anode terminal and the first cathode terminal can be disposed on the first surface of the passive electronic component.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The microelectronic device of claim 1, wherein the insulating element comprises a third intermediate insulating substrate disposed about the capacitor between the first and second insulating substrates.
3. The microelectronic device of claim 1, wherein a coefficient of thermal expansion (CTE) of one or more of the first and second insulating substrates is no more than 5 ppm/° C.
4. The microelectronic device of claim 1, wherein an overall effective coefficient of thermal expansion (CTE) of the microelectronic device is no more than 7 ppm/° C.
5. The microelectronic device of claim 1, further comprising a second interconnect extending through the first non-deposited insulating substrate, the first interconnect connected to a first terminal of the capacitor at a first side of the capacitor and the second interconnect connected to a second terminal at the first side, the first terminal of a different type from the second terminal.
6. The microelectronic device of claim 5, further comprising a third terminal at a second side of the capacitor and a fourth terminal at the second side, the third terminal of a different type from the fourth terminal.
7. A bonded structure comprising the microelectronic device of claim 1 and an element, the element directly bonded to the microelectronic device without an intervening adhesive.
8. A microelectronic device of claim 1, wherein a bottom surface of the first insulating substrate that faces the capacitor comprises a generally planar surface.
9. A microelectronic device of claim 8, wherein an upper surface of the second insulating substrate that faces the capacitor comprises a generally planar surface.
10. A microelectronic device of claim 1, wherein the first interconnect comprises a first portion that extends through the first insulating substrate and a second portion that extends through the insulating element, the first portion disposed directly over the second portion.
13. A microelectronic device of claim 12, wherein at least a portion of the molding compound is partially disposed along the sidewall of the capacitor.
15. The microelectronic device of claim 14, wherein the capacitor is completely embedded within the insulating material.
16. The microelectronic device of claim 14, wherein the insulating material comprises the first adhesive and the second adhesive.
17. The microelectronic device of claim 14, further comprising a molding compound disposed about portions of the capacitor, the insulating material further comprising the molding compound.
18. A microelectronic device of claim 14, wherein the first generally planar non-deposited insulating substrate comprises an interconnect extending through the first generally planar insulating substrate.
19. A microelectronic device of claim 14, wherein the element comprises an integrated device die.
21. The bonded structure of claim 20, wherein the passive electronic component comprises a capacitor.
22. The bonded structure of claim 21, wherein a dielectric material of the capacitor comprises a high K dielectric.
23. The bonded structure of claim 21, wherein the capacitor comprises a serpentine pattern extending through the passive electronic component.
24. The bonded structure of claim 21, wherein the passive electronic component comprises a through-signal conductor extending through the passive electronic component.
25. The bonded structure of claim 20, wherein the element comprises an integrated device die.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 28, 2017
April 11, 2023
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