Semiconductor memory devices and methods of forming the same are provided. The semiconductor devices may include a vertical insulating structure extending in a first direction on a substrate, a semiconductor pattern extending along a sidewall of the vertical insulating structure, a bitline on a first side of the semiconductor pattern, an information storage element on a second side of the semiconductor pattern and including first and second electrodes, and a gate electrode on the semiconductor pattern and extending in a second direction that is different from the first direction. The bitline may extend in the first direction and may be electrically connected to the semiconductor pattern. The first electrode may have a cylindrical shape that extends in the first direction, and the second electrode may extend along a sidewall of the first electrode.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The semiconductor memory device of claim 1, wherein the gate electrode includes an upper gate electrode on a first surface of the semiconductor pattern, a lower gate electrode on a second surface of the semiconductor pattern, and the second surface of the semiconductor pattern is opposite to the first surface of the semiconductor pattern.
4. The semiconductor memory device of claim 1, wherein the bitline includes a vertical portion extending in the first direction, and a horizontal portion protruding from the vertical portion to connect the vertical portion to the semiconductor pattern.
8. The semiconductor memory device of claim 1, wherein the vertical insulating structure extends through the semiconductor pattern.
9. The semiconductor memory device of claim 1, wherein the gate electrode encloses the sidewall of the vertical insulating structure.
10. The semiconductor memory device of claim 1, wherein the semiconductor pattern and the first electrode of the information storage element overlap each other in the second direction.
12. The semiconductor memory device of claim 11, wherein the semiconductor pattern extends on a sidewall of the vertical insulating structure.
15. The semiconductor memory device of claim 11, wherein the information storage element includes a first electrode electrically connected to the semiconductor pattern, a second electrode on the first electrode, and a dielectric film between the first and second electrodes.
16. The semiconductor memory device of claim 15, wherein the first electrode has a closed-loop shape.
17. The semiconductor memory device of claim 11, wherein the semiconductor pattern encloses a sidewall of the vertical insulating structure.
19. The semiconductor memory device of claim 18, wherein the gate electrode includes an upper gate electrode on a first surface of the semiconductor pattern, a lower gate electrode on a second surface of the semiconductor pattern, and the second surface of the semiconductor pattern is opposite to the first surface of the semiconductor pattern.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 29, 2020
April 25, 2023
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