It is an object of the disclosed technique to provide a novel method and system for shared concurrent access to a memory cell. In accordance with the disclosed technique, there is thus provided a system for shared concurrent access to a memory cell, which includes at least one shared memory cell, an evaluator and a plurality of processing agents coupled to the input of the evaluator. The evaluator is further coupled with the at least one memory cell. The evaluator is configured to evaluate an expression for performing multiple concurrent composite assignments on the at least one shared memory cell. The evaluator further allows each of the plurality of processing agents to perform concurrent composite assignments on the at least one shared memory cell. The composite assignments do not include a read operation of the at least one shared memory cell by the plurality of processing agents.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The system according to claim 1, wherein said evaluator performing said multiple concurrent composite assignments is external to said plurality of processing agents.
3. The system according to claim 1, wherein said evaluator enables access to a shared memory cell when allowing said plurality of processing agents to perform concurrent composite assignments on said at least one shared memory cell.
4. The system according to claim 1, wherein the values received by the at least one shared memory cell are the logical ANDs of data to be written with corresponding write enable lines.
5. The system according to claim 1 wherein at least two of said plurality of processing agents are processing threads that are executed concurrently by a single processing core.
6. The system according to claim 1, wherein at least two of said plurality of processing agents are independent processing cores.
7. The system according to claim 1, wherein said evaluator further receiving at the input thereof, via a feedback circuit, a current value of said at least one shared memory cell.
10. The system of claim 9, wherein said at least one memory cell does not include a feedback circuit for receiving a current value of said at least one shared memory cell.
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July 24, 2019
May 9, 2023
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