Instruction processing circuitry comprises fetch circuitry to fetch instructions for execution; instruction decoder circuitry to decode fetched instructions; execution circuitry to execute decoded instructions; and program flow prediction circuitry to predict a next instruction to be fetched; in which the instruction decoder circuitry is configured to decode a loop control instruction in respect of a given program loop and to derive information from the loop control instruction for use by the program flow prediction circuitry to predict program flow for one or more iterations of the given program loop.
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2. The instruction processing circuitry of claim 1, comprising further branch prediction circuitry to predict branch instruction outcomes using data indicative of previously executed branch instructions.
3. The instruction processing circuitry of claim 2, in which, when the information derived from the loop start instruction is flagged as speculative information and the further branch prediction circuitry predicts a branch outcome, the program flow prediction circuitry is configured not to predict a next instruction to be fetched.
4. The instruction processing circuitry of claim 1, in which the program flow prediction circuitry is configured to maintain a counter of loop iterations and to predict termination of the given program loop after a number of loop operations derived from the loop start instruction.
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October 25, 2021
May 16, 2023
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