The present disclosure is directed to methods for the fabrication of gate-all-around (GAA) field effect transistors (FETs) with low power consumption. The method includes depositing a first and a second epitaxial layer on a substrate and etching trench openings in the first and second epitaxial layers and the substrate. The method further includes removing, through the trench openings, portions of the first epitaxial layer to form a gap between the second epitaxial layer and the substrate and depositing, through the trench openings, a first dielectric to fill the gap and form an isolation structure. In addition, the method includes depositing a second dielectric in the trench openings to form trench isolation structures and forming a transistor structure on the second epitaxial layer.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The method of claim 1, wherein replacing the portion of the first epitaxial layer with the dielectric layer comprises forming an air pocket in the dielectric layer and between the substrate and the second epitaxial layer.
4. The method of claim 3, wherein filling the gap with the dielectric layer comprises filling the gap with a flowable chemical vapor deposition C(VD) high aspect ratio process (HARP).
6. The method of claim 1, further comprising recessing an edge portion of the second epitaxial layer adjacent to the superlattice structure such that a top surface of the edge portion is lower than a top surface of a middle portion of the second epitaxial layer below the superlattice structure.
10. The method of claim 9, wherein forming the dielectric layer comprises forming an air pocket in the dielectric layer between the substrate and the second epitaxial layer.
12. The method of claim 11, wherein filling the gap with the dielectric layer comprises filling the gap with a flowable chemical vapor deposition (CVD) high aspect ratio process (HARP).
17. The method of claim 9, further comprising removing an edge portion of the fourth epitaxial layer adjacent to the superlattice structure to expose the second epitaxial layer such that a top surface of the second epitaxial layer is lower than a top surface of a middle portion of the fourth epitaxial layer below the superlattice structure.
19. The structure of claim 18. wherein a width of the first epitaxial layer is less than a width of the dielectric layer.
20. The structure of claim 18, further comprising a source/drain (S/D) region disposed on the edge portion of the second epitaxial layer and adjacent to the superlattice structure.
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February 23, 2022
May 16, 2023
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