Semiconductor devices having improved under-bump metallization layouts and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes an IC die; an interconnect structure coupled to the IC die and including a metallization pattern including a via portion extending through a dielectric layer; a second dielectric layer over the dielectric layer opposite the IC die; and a second metallization pattern coupled to the metallization pattern and including a line portion in the dielectric layer and a second via portion extending through the second dielectric layer; and a UBM over the second metallization pattern and the second dielectric layer, the UBM being coupled to the second metallization pattern, a centerline of the via portion and a second centerline of the second via portion being misaligned with a third centerline of the UBM, the centerline and the second centerline being on opposite sides of the third centerline.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The semiconductor device of claim 1, further comprising a conductive bump coupled to and in physical contact with the UBM.
3. The semiconductor device of claim 1, further comprising a second integrated circuit die coupled to the interconnect structure, the first integrated circuit die comprising a system on chip, the second integrated circuit die comprising a high bandwidth memory die.
4. The semiconductor device of claim 1, wherein a distance between the second centerline and the third centerline in a first direction parallel to a major surface of the second dielectric layer is from 3 μm to 30 μm.
5. The semiconductor device of claim 1, wherein the UBM is disposed in a first region having boundaries aligned with sidewalls of the first integrated circuit die, wherein the third centerline is closer to a fourth centerline of the first region than the second centerline.
6. The semiconductor device of claim 5, further comprising a second UBM, wherein the second metallization pattern further comprises a third via portion extending through the second dielectric layer, the third via portion being coupled to the second UBM, wherein a fifth centerline of the second UBM is disposed further from the fourth centerline of the first region than the third centerline of the UBM, wherein a first distance between the second centerline and the third centerline in a first direction parallel to a major surface of the second dielectric layer is less than a second distance between the fifth centerline and a sixth centerline of the third via portion in the first direction.
7. The semiconductor device of claim 5, further comprising a second UBM, wherein the second metallization pattern further comprises a third via portion extending through the second dielectric layer, the third via portion being coupled to the second UBM, wherein a fifth centerline of the second UBM is disposed further from the fourth centerline of the first region than the third centerline of the UBM, wherein a first distance between the second centerline and the third centerline in a first direction parallel to a major surface of the second dielectric layer is equal to a second distance between the fifth centerline and a sixth centerline of the third via portion in the first direction.
9. The semiconductor device of claim 8, wherein the integrated circuit die comprises a system on chip die.
10. The semiconductor device of claim 8, further comprising a second under-bump metallization extending along the top surface of the top dielectric layer and a top surface of a second via portion of the top metallization pattern, the second under-bump metallization being further from the centerline of the integrated circuit die than the under-bump metallization, wherein a third distance is measured between an edge of the second under-bump metallization closest to the centerline of the integrated circuit die and an edge of the second via portion closest to the centerline of the integrated circuit die, wherein the third distance is greater than the first distance.
11. The semiconductor device of claim 8, further comprising a second under-bump metallization extending along the top surface of the top dielectric layer and a top surface of a second via portion of the top metallization pattern, the second under-bump metallization being further from the centerline of the integrated circuit die than the under-bump metallization, wherein a third distance is measured between an edge of the second under-bump metallization closest to the centerline of the integrated circuit die and an edge of the second via portion closest to the centerline of the integrated circuit die, wherein the third distance is equal to the first distance.
12. The semiconductor device of claim 8, further comprising a plurality of first under-bump metallizations, wherein the first under-bump metallizations comprise the under-bump metallization, and wherein the first under-bump metallizations are evenly spaced relative to one another in a region aligned with sidewalls of the integrated circuit die.
13. The semiconductor device of claim 8, further comprising a plurality of first under-bump metallizations, wherein the first under-bump metallizations are disposed in a region aligned with sidewalls of the integrated circuit die, wherein the region comprises a first portion surrounded by a second portion, and wherein a density of the first under-bump metallizations in the first portion is less than a density of the first under-bump metallizations in the second portion.
14. The semiconductor device of claim 8, further comprising a plurality of first under-bump metallizations, wherein the first under-bump metallizations are disposed in a region aligned with sidewalls of the integrated circuit die, and wherein the first under-bump metallizations are evenly distributed in the region.
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December 31, 2020
May 16, 2023
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