An asymmetrical processing system is provided. The processor has a vector unit comprised of one or more computational units coupled with a vector memory space and a scalar unit coupled with a data memory space and the vector memory space, the scalar unit accessing one or more memory locations within the vector memory space.
Legal claims defining the scope of protection, as filed with the USPTO.
6. The processing system according to claim 5, further comprising a configurable memory access mode to determine a slice or a column memory access mode.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 8, 2015
May 23, 2023
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