A semiconductor package provided. The semiconductor package includes an interposer layer including a first surface and a second surface opposing each other, a first semiconductor chip and a second semiconductor chip on the first surface of the interposer layer, and a block copolymer film on the first semiconductor chip and the second semiconductor chip. The first semiconductor chip and the second semiconductor chip are different from each other. The block copolymer film includes a first pattern and a second pattern, which are different from each other, and one of the first pattern and the second pattern contains graphite.
Legal claims defining the scope of protection, as filed with the USPTO.
5. The semiconductor package of claim 4, wherein the plurality of semiconductor memory chips are electrically connected to each other through a through via extending in the third direction.
7. The semiconductor package of claim 6, wherein the block copolymer film extends along a sidewall of the molding layer, a top surface of the molding layer, and a sidewall of the interposer layer.
16. The semiconductor package of claim 12, wherein the block copolymer film extends to the first surface of the substrate along a side surface of the first semiconductor chip and the side surface of the second semiconductor chip.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 29, 2020
May 23, 2023
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