A chip for hybrid bridged fanout chiplet connectivity, the chip comprising: a central chiplet; one or more first chiplets each coupled to the central chiplet using a plurality of fanout traces; and one or more second chiplets each coupled to the central chiplet using one or more interconnect dies (ICDs).
Legal claims defining the scope of protection, as filed with the USPTO.
2. The chip of claim 1, wherein each of the one or more second chiplets are positioned nearer to the central chiplet relative to the one or more first chiplets.
3. The chip of claim 1, wherein the one or more first chiplets are positioned in a first column of chiplets and the one or more second chiplets are positioned in a second column of chiplets.
4. The chip of claim 1, wherein the one or more first chiplets are positioned in a first row of chiplets and the one or more second chiplets are positioned in a second row of chiplets.
5. The chip of claim 1, wherein the one or more first chiplets are coupled to the central chiplet by a plurality of fanout trace layers layered on a wafer including the central chiplet, the one or more first chiplets, and the one or more second chiplets positioned and fixed using molding.
6. The chip of claim 5, wherein the one or more interconnect dies are bonded to a redistribution layer of the chip layered on the plurality of fanout trace layers.
7. The chip of claim 1, further comprising one or more conductive pillars.
8. The chip of claim 7, further comprising a plurality of caps for the one or more conductive pillars and the one or more interconnect dies (ICDs).
9. The chip of claim 8, wherein the one or more second chiplets include a plurality of second chiplets, the one or more interconnecting dies include a plurality of interconnecting dies, and wherein each of the plurality of second chiplets is coupled to the central chiplet using a respective interconnecting die of the plurality of interconnecting dies.
11. The apparatus of claim 10, wherein each of the one or more second chiplets are positioned nearer to the central chiplet relative to the one or more first chiplets.
12. The apparatus of claim 10, wherein the one or more first chiplets are positioned in a first column of chiplets and the one or more second chiplets are positioned in a second column of chiplets.
13. The apparatus of claim 10, wherein the one or more first chiplets are positioned in a first row of chiplets and the one or more second chiplets are positioned in a second row of chiplets.
14. The apparatus of claim 10, wherein the one or more first chiplets are coupled to the central chiplet by a plurality of fanout trace layers layered on a wafer including the central chiplet, the one or more first chiplets, and the one or more second chiplets positioned and fixed using molding.
15. The apparatus of claim 14, wherein the one or more interconnect dies are bonded to a redistribution layer of the chip layered on the plurality of fanout trace layers.
16. The apparatus of claim 10, wherein the chip comprises one or more conductive pillars.
17. The apparatus of claim 16, further comprising a plurality of caps for the one or more conductive pillars and the one or more interconnect dies (ICDs).
18. The apparatus of claim 10, wherein the one or more second chiplets include a plurality of second chiplets, the one or more interconnecting dies include a plurality of interconnecting dies, and wherein each of the plurality of second chiplets is coupled to the central chiplet using a respective interconnecting die of the plurality of interconnecting dies.
20. The method of claim 19, wherein each of the one or more second chiplets are positioned nearer to the central chiplet relative to the one or more first chiplets.
21. The method of claim 19, wherein the one or more first chiplets are positioned in a first column of chiplets and the one or more second chiplets are positioned in a second column of chiplets.
22. The method of claim 19, wherein the one or more first chiplets are positioned in a first row of chiplets and the one or more second chiplets are positioned in a second row of chiplets.
23. The method of claim 19, wherein coupling, to the central chiplet, the one or more first chiplets comprises layering a plurality of fanout trace layers on a wafer including the central chiplet, the one or more first chiplets, and the one or more second chiplets positioned and fixed using molding.
24. The method of claim 19, wherein coupling, to the central chiplet, the one or more second chiplets comprises bonding the one or more interconnect dies to a redistribution layer of the chip.
25. The method of claim 19, further comprising forming one or more conductive pillars in a layer of the chip.
26. The method of claim 25, further comprising capping the one or more conductive pillars and the one or more interconnect dies.
27. The method of claim 19, wherein the one or more second chiplets include a plurality of second chiplets, the one or more interconnecting dies include a plurality of interconnecting dies, and wherein each of the plurality of second chiplets is coupled to the central chiplet using a respective interconnecting die of the plurality of interconnecting dies.
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September 25, 2020
May 23, 2023
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