A semiconductor memory device includes a substrate, a first conductor layer, and a first insulator layer. The substrate includes a first region on which memory cells are provided, a second region on which a control circuit of the memory cells is provided, and a third region separating the first region and the second region. The first conductor layer is above the second region of the substrate. The first insulator layer is above the second and third regions of the substrate. The first insulator layer includes a first portion that is above the first conductor layer and extends along a surface direction of the substrate, and a second portion that is continuous with the first portion and extends along a thickness direction of the substrate from the first portion toward a surface of the substrate in the third region.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The semiconductor memory device according to claim 1, wherein the first insulator layer is a silicon nitride film.
3. The semiconductor memory device according to claim 1, wherein a thickness of the first insulator layer is uniform between the first portion and the second portion.
5. The semiconductor memory device according to claim 4, wherein each of the first insulator layer and the second insulator layer is a silicon nitride film.
7. The semiconductor memory device according to claim 1, wherein the second portion of the first insulator layer surrounds the first region of the semiconductor substrate.
9. The semiconductor memory device according to claim 8, wherein the second conductor layer serves as a gate electrode of a dummy transistor.
11. The semiconductor memory device according to claim 10, wherein the third portion of the first insulator layer extends through the second conductor layer along the thickness direction of the semiconductor substrate.
14. The semiconductor memory device according to claim 1, wherein the second portion of the first insulator layer contacts the surface of the semiconductor substrate in the third region.
15. The semiconductor memory device according to claim 1, wherein the second portion of the first insulator layer extends into the semiconductor substrate in the third region.
16. The semiconductor memory device according to claim 1, wherein the third region of the semiconductor substrate is a p-well region.
17. The semiconductor memory device according to claim 1, wherein the third region of the semiconductor substrate is an n-well region.
18. The semiconductor memory device according to claim 1, wherein a width of the second portion of the first insulator layer is greater than a width of the first conductor layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 19, 2020
May 30, 2023
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