Disclosed herein are systems and method for instruction tightly-coupled memory (iTIM) and instruction cache (iCache) access prediction. A processor may use a predictor to enable access to the iTIM or the iCache and a particular way (a memory structure) based on a location state and program counter value. The predictor may determine whether to stay in an enabled memory structure, move to and enable a different memory structure, or move to and enable both memory structures. Stay and move predictions may be based on whether a memory structure boundary crossing has occurred due to sequential instruction processing, branch or jump instruction processing, branch resolution, and cache miss processing. The program counter and a location state indicator may use feedback and be updated each instruction-fetch cycle to determine which memory structure(s) needs to be enabled for the next instruction fetch.
Legal claims defining the scope of protection, as filed with the USPTO.
9. The processor of claim 1, wherein the access prediction logic predicts the location state in the location state indicator based on at least: branch resolution processing, branch prediction processing, sequential instruction logic processing, cache hit/miss processing, a previous program counter value, and a previous location state.
18. The method of claim 10, wherein the predicting the instruction fetch location in the location state indicator is based on at least: branch resolution processing, branch prediction processing, sequential instruction logic processing, cache hit/miss processing, a previous program counter value, and a previous location state.
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December 12, 2019
June 27, 2023
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