Patentable/Patents/US-11688557
US-11688557

Capacitor and etching method

PublishedJune 27, 2023
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

According to an embodiment, a capacitor includes a conductive substrate, a conductive layer, a dielectric layer therebetween, and first and second internal electrodes. The substrate has first and second main surfaces. One partial region of the first main surface is provided with first recesses. A region of the second surface corresponding to a combination of the one partial region and another partial region is provided with second recesses. The conductive layer covers the main surfaces and side walls and bottom surfaces of the recesses. The first internal electrode is provided on the one partial region and electrically connected to the conductive layer. The second internal electrode is provided on the another partial region and electrically connected to the substrate.

Patent Claims
2 claims

Legal claims defining the scope of protection, as filed with the USPTO.

2

2. The capacitor according to claim 1, wherein a depth of the one or more second recesses is greater than a depth of the one or more first recesses.

3

3. The capacitor according to claim 1, wherein the one or more first recesses are one or more first trenches, the one or more second recesses are one or more second trenches, a length direction of the one or more first trenches and a length direction of the one or more second trenches intersect each other, and the one or more first trenches and the one or more second trenches are connected to each other at intersections thereof.

Classification Codes (CPC)

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Patent Metadata

Filing Date

August 20, 2020

Publication Date

June 27, 2023

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Cite as: Patentable. “Capacitor and etching method” (US-11688557). https://patentable.app/patents/US-11688557

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