Output buffer having supply filters

2. The electronic device of claim 1, further comprising a resistor coupled between the transistor and the data output.

3. The electronic device of claim 1, wherein the pre-buffer is further configured to receive an enable signal and to be enabled using the enable signal.

5. The electronic device of claim 4, further comprising a memory circuit coupled to the data input.

6. The electronic device of claim 5, wherein the memory circuit comprises a dynamic random access memory (DRAM) circuit or a ferroelectric random access memory (FeRAM) circuit.

7. The electronic device of claim 1, wherein the output stage supply voltage signal provides a supply voltage in a range to 0.5 V to 5 V.

8. The electronic device of claim 7, wherein the supply voltage is 1.8 V.

10. The electronic device of claim 9, wherein the memory circuit comprises a dynamic random access memory (DRAM) circuit.

11. The electronic device of claim 9, wherein the memory circuit comprises a ferroelectric random access memory (FeRAM) circuit.

12. The electronic device of claim 9, wherein the pre-buffer in each output buffer circuit of the multiple output buffer circuits is further configured to receive a respective enable signal of multiple enable signals and to be enabled using the received respective enable signal.

13. The electronic device of claim 9, wherein the output stage supply voltage signal provides a supply voltage in a range to 0.5 V to 5 V.

14. The electronic device of claim 13, wherein the supply voltage is 1.8 V.

15. The electronic device of claim 9, wherein the low-pass filter comprises a resistor and a capacitor.

17. The method of claim 16, further comprising powering additional one or more pre-buffers of one or more additional output buffers using the filtered supply voltage signal.

19. The method of claim 16, wherein using the low-pass filter comprises using a low-pass filter formed by a resistor and a capacitor.

20. The method of claim 16, further comprising using the pre-buffer and the transistor in an output buffer of a dynamic random access memory (DRAM) device or a ferroelectric random access memory (FeRAM) device.