Adaptive memory cell write conditions

2. The memory device of claim 1, wherein the array of memory cells comprises random access memory (RRAM) cells.

3. The memory device of claim 1, wherein the read sense circuit is a read sense amplifier, wherein the read sense amplifier directly measures the current resulting from the application of the voltage.

4. The memory device of claim 1, wherein the write condition selector circuit determines a number of the one or more pulses to be transmitted to the selected memory cell based on the resistance associated with the selected memory cell.

5. The memory device of claim 1, wherein the write condition selector circuit determines pulse widths of the one or more pulses to be transmitted to the selected memory cell based on the resistance associated with the selected memory cell and limits currents associated with the one or more pulses as seen by the selected memory cell.

7. The memory device of claim 6, wherein the write driver generates the one or more pulses to be transmitted to the selected memory cell.

8. The memory device of claim 7, wherein the one or more pulses are generated by a pulse generator of the write driver.

9. The memory device of claim 6, wherein the write driver generates a word line voltage signal to limit the currents associated with the one or more pulses as seen by the selected memory cell.

10. The memory device of claim 9, wherein the currents associated with the one or more pulses are limited by a wordline voltage generator of the write driver.

12. The memory device of claim 11, wherein the input of the A/D converter is coupled to the selected memory cell through at least one multiplexer.

13. The memory device of claim 11, wherein the logic includes logic gates implementing a state machine.

14. The memory device of claim 13, wherein the lookup table stores data relating to memory cell current, memory cell voltage, timing, word line voltage, and current limit.

15. The memory device of claim 14, wherein the memory cell current, memory cell voltage, timing, word line voltage, and current limit are determined based on operations of the array of memory cells.

16. The memory device of claim 14, wherein the A/D converter outputs a digital value to the logic based on the resistance associated with the selected memory cell.

17. The memory device of claim 16, wherein the logic generates a control signal to the write driver to generate the one or more pulses based on the digital value outputted by the A/D converter using the lookup table.

18. The memory device of claim 16, wherein the logic generates a control signal to the write driver to generate a word line voltage signal to limit the currents associated with the one or more pulses based on the digital value outputted by the A/D converter using the lookup table.