Integrated passive device and fabrication method using a last through-substrate via

4. The method of claim 1, wherein the forming the TSV includes a two-step etching process with a first etch to etch a substrate portion of the TSV and a second etch to etch an insulator material portion of the TSV.

5. The method of claim 1, wherein an insulator material cavity formed by the TSV extends to a depth of at least 5 μm in the insulator material from the front surface of the substrate to expose the at least one of the two device terminals to of the device body that is at least partially embedded in the insulator material.

8. The method of claim 6, wherein an insulator material cavity extends to a depth of at least 5 μm in the insulator material from the front surface of the substrate to expose the at least one of the two device terminals connected to the device body that is at least partially embedded in the insulator material.

10. The method of claim 9, wherein the at least one passive component includes at least one of an inductor, a resistor, or a capacitor having a terminal embedded in the insulator material layer.

11. The method of claim 9, wherein the grinding the backside of the substrate includes using a grind process that thins the central portion of the substrate to be at least three-quarters or less of an original thickness.

12. The method of claim 11, wherein etching through the portion of the insulator material layer exposes a terminal of the at least one passive component embedded in the insulator material layer.

13. The method of claim 11, further comprising, grinding the mechanical support ring on the outer portion of the substrate to a reduced height.

14. The method of claim 9, wherein etching through the thickness of the semiconductor substrate and etching through the portion of the insulator material layer includes etching a tapered TSV, the tapered TSV having a tapered wall sloping in from a wider surface opening to a narrower TSV bottom.

16. The method of claim 15, wherein the forming the plated copper layer on the backside of the substrate and in the TSV along the tapered wall and over the TSV bottom includes depositing a titanium-copper (Ti—Cu) barrier and seed layer on the backside of the substrate and in the TSV along the tapered wall.

17. The method of claim 15, wherein the forming the plated copper layer on the backside of the substrate and in the TSV along the tapered wall and over the TSV bottom includes growing an oxide layer on the backside of the substrate and then the plated copper layer.

18. The method of claim 15, further comprising, applying an under bump metal (UBM) etch to the plated copper layer.