Legal claims defining the scope of protection, as filed with the USPTO.
2. The semiconductor device of claim 1, wherein the portion of the gate dielectric layer is directly under a top surface of the first portion.
3. The semiconductor device of claim 1, wherein the portion of the gate dielectric layer is directly under a portion of the semiconductor oxide feature.
4. The semiconductor device of claim 1, wherein the portion of the gate dielectric layer is directly under the interfacial layer.
5. The semiconductor device of claim 1, wherein the interfacial layer is in physical contact with a top surface of the first portion.
6. The semiconductor device of claim 1, wherein a bottommost portion of the interfacial layer is above a top surface of the first portion.
8. The semiconductor device of claim 1, wherein the gate dielectric layer extends into recesses that are into a top portion of the semiconductor oxide feature.
9. The semiconductor device of claim 8, wherein the gate stack further includes a gate electrode disposed on the gate dielectric layer and a portion of the gate electrode also extends into the recesses.
11. The semiconductor structure of claim 10, wherein the second lattice constant is less than the first lattice constant.
12. The semiconductor structure of claim 10, wherein the first portion of the fin feature has a largest thickness at the top surface.
13. The semiconductor structure of claim 10, wherein a topmost portion of the semiconductor oxide feature is below the bottom surface of the second portion of the fin feature.
14. The semiconductor structure of claim 10, wherein a top surface of the isolation feature is below the top surface of the first portion of the fin feature.
15. The semiconductor structure of claim 10, wherein the gate stack includes an interfacial layer in physical contact with the top surface of the first portion of the fin feature but not in physical contact with the concave sidewall of the first portion of the fin feature.
17. The semiconductor device of claim 16, wherein the interfacial layer is free of contact with the recessed sidewalls of the first portion.
18. The semiconductor device of claim 16, wherein a bottommost portion of the interfacial layer is above the top surface of the first portion.
19. The semiconductor device of claim 18, wherein a portion of the gate dielectric layer is below the top surface of the first portion.
20. The semiconductor device of claim 16, wherein a portion of the gate dielectric layer is directly under the top surface of the first portion.
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August 22, 2023
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