Methods of forming microelectronic devices, and related microelectronic devices, memory devices, and electronic systems

5. The method of claim 1, wherein forming a second control logic region over the first memory array region comprises forming transistors of the second control logic devices partially within and from the remaining portion of the semiconductive material.

6. The method of claim 1, wherein forming a second control logic region over the first memory array region comprises forming the second control logic devices of the second control logic region to have different configurations and operational functions than the first control logic devices of the first control logic region.

7. The method of claim 6, wherein forming the second control logic devices of the second control logic region to have different configurations and operational functions than the first control logic devices of the first control logic region comprises forming the second control logic devices to operate at applied voltages within a range of from about 0.7V to about 1.4 V.

8. The method of claim 7, further comprising forming the first control logic devices of the first control logic region to comprise additional CMOS circuitry configured to operate at other applied voltages greater than the applied voltages effective to operate of the second control logic devices of the second control logic region.

9. The method of claim 1, wherein forming a second memory array region over the second control logic region comprises forming the array of resistance variable memory cells of the second memory array region to be in electrical communication with the second control logic devices of the second control logic region and the first control logic devices of the first control logic region.

13. The microelectronic device of claim 11, wherein the second control logic devices of the second control logic region are configured to effectuate different operational functions for the vertically extending strings of memory cells of the first memory array region and the resistance variable memory cells of the second memory array region than the first control logic devices of the first control logic region.

15. The microelectronic device of claim 11, wherein each memory cell of the vertically extending strings of memory cells of the first memory array region comprises a metal-oxide-nitride-oxide-semiconductor (MONOS) memory cell.

16. The microelectronic device of claim 11, wherein each resistance variable memory cell of the second memory array region comprises a storage element comprising a solid state electrolyte material.

17. The microelectronic device of claim 16, wherein the solid state electrolyte material comprises a chalcogenide material.

23. The memory device of claim 22, wherein the at least one source structure, the digit line structures, the first conductive line structures, and the second conductive line structures are in electrical communication with the control logic devices and the additional control logic devices.