Patentable/Patents/US-11784164
US-11784164

3D stacked compute and memory with copper-to-copper hybrid bond

PublishedOctober 10, 2023
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

Patent Claims
17 claims

Legal claims defining the scope of protection, as filed with the USPTO.

2

2. The processor system of claim 1, wherein the copper-to-copper hybrid bond is associated with TSVs of the first die or the second die, and wherein the copper-to-copper hybrid bond allows the TSVs to have a tighter pitch compared to without copper-to-copper hybrid bond.

3

3. The processor system of claim 1, wherein active devices of the second die face the first die.

4

4. The processor system of claim 2, wherein the TSVs of the first die or the second die include a first TSV and a second TSV, and wherein the first TSV carries power and the second TSV carries data.

5

5. The processor system of claim 1, wherein the first die is on the second die.

6

6. The processor system of claim 1, wherein the second die is on the first die.

7

7. The processor system of claim 1, wherein the first memory type is same as the second memory type.

8

8. The processor system of claim 1, wherein the first memory type is different from the second memory type.

9

9. The processor system of claim 1, wherein the first memory type and the second memory type comprise ferroelectric material.

10

10. The processor system of claim 1, wherein the first die comprises ferroelectric logic and/or paraelectric material.

11

11. The processor system of claim 1, wherein the first die comprises ferroelectric logic and ferroelectric memory.

12

12. The processor system of claim 1, wherein the second memory comprises ferroelectric material, wherein the first memory comprises SRAM.

13

13. The processor system of claim 1, wherein the first memory and the second memory comprise SRAM.

14

14. The processor system of claim 1 comprises a heat spreader over the stack of dies.

16

16. The processor system of claim 15, wherein the first die or the second die includes processor cores.

19

19. The method of claim 18, wherein the copper-to-copper hybrid bond is associated with TSVs of the first die or the second die, and wherein the copper-to-copper hybrid bond allows the TSVs to have a tighter pitch compared to without copper-to-copper hybrid bond.

20

20. The method of claim 19, wherein the TSVs of the first die or the second die include a first TSV and a second TSV, and wherein the first TSV carries power and the second TSV carries data.

21

21. The method of claim 18, wherein active devices of the second die face the first die.

Patent Metadata

Filing Date

Unknown

Publication Date

October 10, 2023

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Cite as: Patentable. “3D stacked compute and memory with copper-to-copper hybrid bond” (US-11784164). https://patentable.app/patents/US-11784164

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