Semiconductor device and method of manufacturing

3. The method of claim 2, wherein the plasma comprises oxygen, nitrogen, fluorine, or chlorine.

4. The method of claim 1, wherein the treating the first dielectric layer further comprises annealing the first dielectric layer.

5. The method of claim 4, wherein the annealing is performed in an oxygen environment.

6. The method of claim 1, wherein the recovered layer has a first thickness, the first dielectric layer has a second thickness, and the first thickness is between 5% and 30% of the second thickness.

7. The method of claim 1, further comprising patterning the gate electrode material into a first gate electrode over the recovered layer and a second gate electrode over the second dielectric layer, the first gate electrode having a larger width than the second gate electrode.

9. The method of claim 8, further comprising replacing the first gate electrode and the second gate electrode.

10. The method of claim 8, wherein the first plasma comprises an oxygen plasma.

11. The method of claim 8, wherein the first plasma comprises a chlorine plasma.

12. The method of claim 8, wherein the first plasma comprises a nitrogen plasma.

13. The method of claim 8, wherein a first thickness of the recovered region is less than 30% of a second thickness of the first dielectric layer.

14. The method of claim 8, wherein the first region is a logic region and the second region is an analog region.

16. The method of claim 15, wherein after the forming the analog device a first top surface of the first gate electrode is a first distance away from the substrate and wherein a second top surface of the second gate electrode is located a second distance away from the substrate, the second distance being greater than the first distance.

17. The method of claim 15, wherein after the forming the analog device a first top surface of the first gate electrode is a first distance away from the substrate and wherein a second top surface of the second gate electrode is located the first distance away from the substrate.

18. The method of claim 15, further comprising forming a first high-k dielectric layer after the forming the second dielectric layer and prior to the forming the second gate electrode, wherein the first high-k dielectric layer extends along multiple sides of the second gate electrode.

19. The method of claim 15, further comprising forming a first high-k dielectric layer after the forming the second dielectric layer and prior to the forming the second gate electrode, wherein the second gate electrode is in physical contact with a spacer.

20. The method of claim 15, wherein after the forming the analog device the second gate electrode has a width that is larger than the first gate electrode.