Semiconductor package

3. The semiconductor package of claim 1, wherein the distance between the outer side surface of the spacer and the third side surface of the lowermost second semiconductor chip in the first direction ranges from 10 μm to 500 μm.

4. The semiconductor package of claim 1, wherein, when viewed in a plan view, an area of the spacer is smaller than an area of the lowermost second semiconductor chip, and an area of the first semiconductor chip is smaller than the area of the lowermost second semiconductor chip.

5. The semiconductor package of claim 1, wherein, when viewed in a plan view, the spacer has a width in a second direction that is parallel to the substrate and is perpendicular to the first direction; and wherein the width of the spacer in the second direction is smaller than a width of the lowermost second semiconductor chip in the second direction.

6. The semiconductor package of claim 1, wherein the spacer comprises an insulating material.

7. The semiconductor package of claim 1, further comprising adhesive layers interposed between the spacer and the substrate, between the first semiconductor chip and the substrate, between the lowermost second semiconductor chip and each of the spacer and the first semiconductor chip, and between the second semiconductor chips.

10. The device of claim 9, wherein an overhang between the portion of the stack of second semiconductor chips and the at least one sidewall is in a range from 10 μm to 500 μm.

11. The device of claim 9, wherein 0.8(L3)≤L1≤0.99(L3).

12. The device of claim 9, wherein the spacer comprises an electrically insulating material.