Resistive memory apparatus

2. The resistive memory apparatus of claim 1, wherein when one of the memory elements is selected as a select memory element, the select circuit coupled to the select memory element via the bit line selects the coupled bit line, and other select circuits select the coupled bypass paths.

3. The resistive memory apparatus of claim 2, wherein each of the select circuits comprises a first switch element and a second switch element, the first switch element is disposed on the corresponding bit line, the second switch element is disposed on the corresponding bypass path, and one end of the first switch element and one end of the second switch element are commonly coupled to the second node on the corresponding bit line.

4. The resistive memory apparatus of claim 3, wherein when the select memory element is selected, the first switch element disposed on the bit line corresponding to the select memory element is turned on, and the second switch element disposed on the bypass path connected in parallel to the bit line corresponding to the select memory element is turned off.

5. The resistive memory apparatus of claim 3, wherein when the select memory element is selected, the first switch element disposed on the bit lines corresponding to other memory elements is turned off, and the second switch element disposed on the bypass paths connected in parallel to the bit lines corresponding to the other memory elements is turned on.

6. The resistive memory apparatus of claim 2, wherein the switch circuit comprises a plurality of third switch elements, one end of the third switch elements is respectively coupled to the word lines, and another end of the third switch elements is coupled to a source line.

7. The resistive memory apparatus of claim 6, wherein when the select memory element is selected, the third switch element coupled to the word line corresponding to the select memory element is turned on.

8. The resistive memory apparatus of claim 1, wherein each of the memory elements comprises a resistive memory cell and a selector.

9. The resistive memory apparatus of claim 8, wherein the selector is an ovonic threshold switch (OTS) that is a two-terminal symmetrical voltage-sensitive switching element.

10. The resistive memory apparatus of claim 8, wherein the selector is based on field-enhanced emission.

11. The resistive memory apparatus of claim 8, wherein the selector is based on tunneling.

12. The resistive memory apparatus of claim 8, wherein the selector is integrated into the resistive memory cell.

14. The resistive memory apparatus of claim 8, wherein the selector allows two-way switching.