Integrated circuit having vertical routing to bond pads

2. The assembly according to claim 1, wherein vertical routing of the IO signal connections in the second wafer comprises vias from metal layer to metal layer.

3. The assembly according to claim 1, wherein the IO pads on the backside layer are located on a metal layer in the second wafer closest to the backside surface of the assembly.

4. The assembly according to claim 1, wherein the first wafer includes a readout integrated circuit (ROIC) substrate, and the second wafer comprises a charge coupled device (CCD) substrate.

5. The assembly according to claim 4, further including at least one backside layer including an anti-reflective coating layer and a backside metal layer.

6. The assembly according to claim 1, wherein the IO pads on a backside surface of the assembly are exposed by etching material from the backside layer of the assembly.

7. The assembly according to claim 6, wherein the IO pads on the backside layer are located on a metal layer in the second wafer closest to the backside surface of the assembly.

8. The assembly according to claim 6, further including an external electrical connection to making an external connection to the IO pads.