Approach for reducing side effects of computation offload to memory

2. The cache controller of claim 1, wherein the cache controller is further configured to cause the at least a portion of the memory-side processing results to be loaded into a particular processor-side cache that is specified by the memory-side processing command.

5. The cache controller of claim 1, wherein the cache controller is further configured to determine that at least the portion of the memory-side processing results will be read by a processor based upon at least the portion of the memory-side processing results being in an address range programmed in the cache controller and the memory-side processing command specifying that at least the portion of the memory-side processing results should be loaded into the processor-side cache.

9. The cache controller of claim 1, wherein the cache controller is further configured to enforce an ordering constraint to ensure that the at least a portion of the memory-side processing results are loaded into the processor-side cache after the at least a portion of the memory-side processing results have been completed and stored to memory.

11. The memory controller of claim 10, wherein the memory controller is further configured to cause the at least a portion of the memory-side processing results to be loaded into a particular processor-side cache that is specified by the memory-side processing command.

14. The memory controller of claim 10, wherein the memory controller is further configured to determine that at least the portion of the memory-side processing results will be read by a processor based upon at least the portion of the memory-side processing results being in an address range programmed in the memory controller and the memory-side processing command specifying that at least the portion of the memory-side processing results should be loaded into the processor-side cache.

18. The memory controller of claim 10, wherein the memory controller is further configured to enforce an ordering constraint to ensure that the at least a portion of the memory-side processing results are loaded into the processor-side cache after the at least a portion of the memory-side processing results have been completed and stored to memory.

20. The method of claim 19, further comprising causing, by the cache controller, the at least a portion of the memory-side processing results to be loaded into a particular processor-side cache that is specified by the memory-side processing command.