Memory device and reference circuit thereof

3. The device of claim 2, wherein the first logic data and the second logic data are different from each other.

12. The method of claim 11, wherein the switch is turned on in response to a selection signal during a read operation.

15. The device of claim 13, wherein the first reference storage unit and the second reference storage unit have different logic states.

19. The device of claim 13, wherein the second reference switch is coupled between a second reference bit line and the second reference storage unit.

20. The method of claim 8, wherein second terminals of the plurality of reference switches are coupled together to a reference bit line.