Patentable/Patents/US-11848205
US-11848205

Semiconductor structure and manufacturing method therefor

PublishedDecember 19, 2023
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

Patent Claims
17 claims

Legal claims defining the scope of protection, as filed with the USPTO.

2

2. The semiconductor structure according to claim 1, wherein the second buffer layer is co-doped with the transition metal, C and an n-type impurity, a doping concentration of C is not greater than the doping concentration of the transition metal, and a doping concentration of the n-type impurity is not greater than sum of the doping concentration of C and the doping concentration of the transition metal.

3

3. The semiconductor structure according to claim 1, wherein the doping concentration of the transition metal in the second buffer layer decreases along a direction away from the substrate.

4

4. The semiconductor structure according to claim 1, wherein the doping concentration of the transition metal is IE17 cm-3 to IE19 cm-3 in the first buffer layer.

5

5. The semiconductor structure according to claim 1, wherein the doping concentration of C is 5E15 cm-3 to 5E18 cm-3 in the first buffer layer.

6

6. The semiconductor structure according to claim 1, wherein the doping concentration of the n-type impurity is IE15 cm-3 to 2E18 cm-3 in the first buffer layer.

7

7. The semiconductor structure according to claim 1, wherein the transition metal comprises at least one of Ti, Cr, Mn, Fe, Co, Ni, Cu, Zn, MO, Ag and Cd.

8

8. The semiconductor structure according to claim 1, wherein the n-type impurity includes at least one of Si, Ge and O.

9

9. The semiconductor structure according to claim 1, wherein a thickness of the first buffer layer is 0.01 gm to 5 gm, and a thickness of the second buffer layer is 0.05 gm to 5 gm.

10

10. The semiconductor structure according to claim 1, wherein the substrate is made of semiconductor materials, ceramic materials or polymer materials, and further made of sapphire, silicon carbide, silicon, lithium niobate, silicon on insulator, gallium nitride and aluminum nitride.

11

11. The semiconductor structure according to claim 1, further comprising a nucleating layer disposed between the substrate and the buffer layer.

12

12. The semiconductor structure according to claim 11, wherein the nucleating layer is made of one of AIN, GaN and AlGaN.

14

14. The manufacturing method for the semiconductor structure according to claim 13, wherein the second buffer layer is co-doped with the transition metal, C and an n-type impurity, a doping concentration of C is not greater than the doping concentration of the transition metal, and a doping concentration of the n-type impurity is not greater than sum of the doping concentration of C and the doping concentration of the transition metal.

15

15. The manufacturing method for the semiconductor structure according to claim 13, wherein the doping concentration of the transition metal in the second buffer layer decreases along a direction away from the substrate.

16

16. The manufacturing method for the semiconductor structure according to claim 13, wherein the doping concentration of the transition metal is IE17 cm-3 to IE19 cm-3 in the first buffer layer.

17

17. The manufacturing method for the semiconductor structure according to claim 13, wherein the doping concentration of C is 5E15 cm-3 to 5E18 cm-3 in the first buffer layer.

18

18. The manufacturing method for the semiconductor structure according to claim 13, wherein the doping concentration of the n-type impurity is I EI 5 cm-3 to 2E18 cm-3 in the first buffer layer.

20

20. The manufacturing method for the semiconductor structure according to claim 19, wherein the nucleating layer is made of one of AIN, GaN and AlGaN.

Patent Metadata

Filing Date

Unknown

Publication Date

December 19, 2023

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