Techniques to create power connections from floating nets in standard cells

2. The integrated circuit as recited in claim 1, wherein the first signal route provides one of a power supply voltage reference level and a ground reference voltage level used by the integrated circuit.

3. The integrated circuit as recited in claim 2, wherein the third signal route has a physical connection to a source region of a transistor in the standard cell.

4. The integrated circuit as recited in claim 2, further comprising one or more tracks of the first metal layer between the first signal route and the second signal route.

5. The integrated circuit as recited in claim 1, further comprising one or more floating signal routes of the first metal layer with no connection to a power supply voltage reference level or a ground reference voltage level used by the integrated circuit.

6. The integrated circuit as recited in claim 1, wherein one or more of the first signal route, the second signal route, and the third signal route are unidirectional signal routes.

7. The integrated circuit as recited in claim 1, wherein the third signal route is orthogonal to the first signal route.

9. The method as recited in claim 8, wherein the first signal route provides one of a power supply voltage reference level and a ground reference voltage level used by the integrated circuit.

10. The method as recited in claim 9, wherein the third signal route has a physical connection to a source region of a transistor in the standard cell.

11. The method as recited in claim 9, further comprising forming, in the integrated circuit, one or more tracks of the first metal layer between the first signal route and the second signal route.

12. The method as recited in claim 8, further comprising forming, in the integrated circuit, one or more floating signal routes of the first metal layer with no connection to a power supply voltage reference level or a ground reference voltage level used by the integrated circuit.

13. The method as recited in claim 8, wherein one or more of the first signal route, the second signal route, and the third signal route are unidirectional signal routes.

14. The method as recited in claim 8, wherein the third signal route is orthogonal to the first signal route.

16. The computing system as recited in claim 15, wherein the first signal route provides one of a power supply voltage reference level and a ground reference voltage level used by the integrated circuit.

17. The computing system as recited in claim 16, wherein the third signal route has a physical connection to a source region of a transistor in the standard cell.

18. The computing system as recited in claim 16, wherein the integrated circuit further comprises one or more tracks of the first metal layer between the first signal route and the second signal route.

19. The computing system as recited in claim 15, wherein the integrated circuit further comprises one or more floating signal routes of the first metal layer with no connection to a power supply voltage reference level or a ground reference voltage level used by the integrated circuit.

20. The computing system as recited in claim 15, wherein one or more of the first signal route, the second signal route, and the third signal route are unidirectional signal routes.