Legal claims defining the scope of protection, as filed with the USPTO.
2. The semiconductor package of claim 1, wherein the horizontal length of e overhang fs about 30 μm to about 90 μm.
3. The semiconductor package of claim 1, wherein the overhang has a rectangular frame shape extended along the edge portion of the second semiconductor chip.
4. The semiconductor package of claim 1, further comprising an upper insulation layer disposed on the upper surface of the first semiconductor chip, the upper insulation layer having openings exposing the upper ends of the connection vias.
5. The semiconductor package of claim 4, wherein the upper insulation layer is disposed on the central portion of the upper surface of the first semiconductor chip.
6. The semiconductor package of claim 5, wherein the upper insulation layer is disposed on the edge portion of the upper surface of the first semiconductor chip.
7. The semiconductor package of claim 1, wherein the molding member fills a space between the overhang and the edge portion of the upper surface of the first semiconductor chip.
8. The semiconductor package of claim 1, further comprising conductive bumps mounted on the wiring.
10. The semiconductor package of claim 9, wherein the groove has a width that is substantially the same as a width of the peripheral region.
11. The semiconductor package of claim 9, wherein the groove has a width that is narrower than a width of the peripheral region.
12. The semiconductor package of claim 11, wherein the groove is extended from a side surface of the bonding region.
14. The semiconductor package of claim 13, wherein the second semiconductor chip comprises a plurality of bonding pads disposed on a lower surface of the second semiconductor chip and directly connected to the upper ends of the plurality of connection vias.
15. The semiconductor package of claim 9, wherein the bonding region is a central portion of the upper surface of the first semiconductor chip, and the peripheral region at least partially surrounds the bonding region.
16. The semiconductor package of claim 9, wherein the overhang is horizontally protruded from the bonding region.
17. The semiconductor package of claim 16, wherein the overhang has a horizontal length of about 3/20 times to about 9/20 times a width of the second semiconductor chip.
18. The semiconductor package of claim 16, wherein a distance between a lower surface of the overhang and a bottom surface of the groove is no less than about 8 μm.
19. The semiconductor package of claim 16, wherein the overhang has a rectangular frame shape at least partially surrounding four side surfaces of the second semiconductor chip.
20. The semiconductor package of claim 19, wherein the upper insulation layer is disposed on an upper surface of the bonding region in the first semiconductor chip.
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December 26, 2023
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