A memory system includes a plurality of non-volatile memory chips and a controller configured to communicate with a host and control the plurality of non-volatile memory chips. The controller is configured to write a data frame that includes write data and a first parity for error detection and correction of the write data into first memory chips of the non-volatile memory chips in a distributed manner. The first memory chips includes N (N is a natural number of two or more) memory chips. The controller is configured to write a second parity for restoring data stored in one of the N first memory chips using data read from the other N−1 of the N first memory chips, into a second memory chip of the non-volatile memory chips that is different from any of the first memory chips.
Legal claims defining the scope of protection, as filed with the USPTO.
3. The memory system according to claim 1, wherein the first parity is a Bose-Chaudhuri-Hocquenghem (BCH) code.
5. The memory system according to claim 3, wherein the second parity includes a bit XOR of data portions of the data frame that are written into the first N memory chips in the distributed manner.
9. The memory system according to claim 1, wherein the non-volatile memory chips are phase-change memories (PCM), magnetoresistive random access memories (MRAM), resistive RAMs (ReRAM), or ferroelectric RAMs (FeRAM).
13. The memory system according to claim 10, wherein the first parity is a Bose-Chaudhuri-Hocquenghem (BCH) code.
16. The memory system according to claim 15, wherein when the calculation of error bit positions for the second data frame is successful, the controller does not execute the calculation of error bit positions for the third data frame.
17. The memory system according to claim 13, wherein the second parity includes a bit XOR of data portions of the data frame that are written into the first N memory chips in the distributed manner.
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February 24, 2022
January 2, 2024
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