Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including performing a read operation on a block of the memory device by applying a read reference voltage to a selected wordline of the block and applying a pass-through voltage having a first value to a plurality of unselected wordlines of the block; detecting a read error in response to performing the read operation; and setting the pass-through voltage to a second value, wherein the second value is greater than the first value.
Legal claims defining the scope of protection, as filed with the USPTO.
6. The system of claim 5, wherein detecting the read reference voltage calibration event comprises detecting a block family associated with the block being assigned to a new predefined threshold voltage offset bin.
7. The system of claim 5, wherein detecting the read reference voltage calibration event comprises detecting a time after programming (TAP) value of the block exceeding a threshold criterion.
14. The method of claim 13, wherein detecting the read reference voltage calibration event comprises detecting a block family associated with the block being assigned to a new predefined threshold voltage offset bin.
15. The method of claim 13, wherein detecting the read reference voltage calibration event comprises detecting a time after programming (TAP) value of the block exceeding a threshold criterion.
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August 17, 2022
January 9, 2024
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