In some embodiments, a system comprises a static random access memory (SRAM) device and a controller. The SRAM device comprises a bit cell array comprising a plurality of bit cells arranged in a plurality of rows and a plurality of columns, each column operatively coupled to a pair of bit lines, wherein the plurality of columns is arranged as a plurality of column groups each comprising a plurality of local columns. The SRAM device further comprises a plurality of column decoders, each associated with a column group of the plurality of column groups. In some embodiments, the controller may be configured to read the local columns included in the column group by, for a given local column, sensing a voltage difference on a corresponding pair of bit lines, in a rearranged sequential order that is different from a physical sequential order of the plurality of local columns.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The system of claim 1, wherein the rearranged sequential order is determined based at least in part on a reorder signal obtained by the controller.
3. The system of claim 2, wherein the reorder signal is a binary signal.
4. The system of claim 3, wherein the sequential order is a reverse of the physical sequential order.
5. The system of claim 4, wherein the sequential order is determined based on an exclusive OR (XOR) operation of the reorder signal with bits of the column addresses associated with the local columns.
6. The system of claim 1, wherein sensing the voltage difference on the corresponding pair of bit lines in the sequential order that is different from the physical sequential order of the plurality of local columns comprises sensing the voltage difference of a pair of bit lines associated with a local column having a first access time prior to sensing the voltage difference of a pair of bit lines associated with a local column having a second access time, the second access time being longer than the first access time.
7. The system of claim 1, wherein the controller is further configured to provide a row address to the row decoder that causes the word line corresponding to the row of the plurality of rows associated with the row address to be asserted prior to reading the local columns of the plurality of local columns.
8. The system of claim 7, wherein the controller is further configured to de-assert the word line after the local columns have been read in the rearranged sequential order.
9. The system of claim 1, wherein a signal representative of the rearranged sequential order is utilized by a column multiplexer to select local columns of the plurality of local columns in the rearranged sequential order.
11. The system of claim 10, wherein a row of the first bit cell of the redundant column is the same as a row of the faulty bit cell of the first local column.
12. The system of claim 10, wherein mapping the row address, the column group identifier, and the local column address to the repaired address comprises obtaining the repaired address from a look up table by providing the row address, the column group identifier, and the local column address to the look up table.
13. The system of claim 12, wherein the look up table is pre-configured based on testing of the SRAM device.
14. The system of claim 12, wherein the look up table is operatively coupled to a multiplexer configured to select the redundant column corresponding to the repaired address.
15. The system of claim 10, wherein the one or more redundant columns comprise at least two redundant columns, and wherein the at least two redundant columns are associated with different column groups of the plurality of column groups.
16. The system of claim 10, wherein the controller is further configured to pre-charge a set of bit lines corresponding to a plurality of local columns included in a column group corresponding to the column group identifier, and wherein mapping the row address, the column group identifier, and the local column address to the repaired address occurs concurrently with the pre-charging the set of bit lines.
17. The system of claim 10, wherein mapping the row address, the column group identifier, and the local column address to the repaired address occurs concurrently with the word line being asserted.
18. The system of claim 10, wherein at least one local column of the column group associated with the column group identifier does not have a corresponding redundant column included in the one or more redundant columns.
20. The system of claim 19, wherein causing the delay of at least the subset of memory access operations is responsive to enabling of a stall signal, and wherein performing the at least the subset of the memory access operations after the time period associated with the delay has elapsed is responsive to disabling the stall signals.
21. The system of claim 20, wherein enabling the stall signal and disabling the stall signal is performed using a handshaking protocol associated with performing the series of memory access operations.
22. The system of claim 21, wherein the handshaking protocol is associated with a row stride and/or a column stride for performing the series of memory access operations.
23. The system of claim 19, wherein the series of memory access operations comprise a series of read operations.
24. The system of claim 23, wherein pre-charging of the one or more bit lines is extended during the time period.
25. The system of claim 23, wherein the at least the subset of memory access operations comprises all of the memory access operations in the series of memory access operations.
26. The system of claim 19, wherein the series of memory access operations comprise a series of write operations.
27. The system of claim 26, wherein the slow bit line is driven during the time period.
28. The system of claim 26, wherein the at least the subset of memory access operations comprises memory access operations subsequent to access of the local column associated with the slow bit line.
29. The system of claim 19, wherein the time period corresponds to a clock cycle.
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April 11, 2022
January 9, 2024
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