Some memory dies in a stack can be connected externally to the stack and other memory dies in the stack can be connected internally to the stack. The memory dies that are connected externally can act as interface dies for other memory dies that are connected internally thereto. The external connections can be used for transmitting signals indicative of data to and/or from the memory dies while the memory dies in the stack can be connected by a cascading connection for transmission of other signals such as command, address, power, ground, etc.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The apparatus of claim 1, wherein the substrate further comprises control circuitry configured to control data transfers with the first, second, third, and fourth memory dies via the first and the third memory dies as a single channel.
6. The apparatus of claim 4, wherein the first, the second, the third, and the fourth CA links further comprise power and ground connections for the first, the second, the third, and the fourth memory dies.
11. The method of claim 9, further comprising receiving power at the first memory die via a command/address (CA) link.
12. The method of claim 11, further comprising receiving a CA signal at the first memory die via the CA link.
15. The method of claim 9, further comprising sending the signals indicative of the first, second, third, fourth, fifth, sixth, seventh, and eighth data without including a timing bubble between the first, the second, the third, or the fourth portions of burst.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 15, 2021
January 9, 2024
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