A semiconductor package structure includes a first semiconductor wafer including a first bonding pad. The semiconductor package structure also includes a second semiconductor wafer including a second bonding pad and a third bonding pad. The second bonding pad and the third bonding pad are bonded to the first bonding pad of the first semiconductor wafer. The semiconductor package structure further includes a first via penetrating through the second semiconductor wafer to physically contact the first bonding pad of the first semiconductor wafer. A portion of the first via is disposed between the second bonding pad and the third bonding pad.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The semiconductor package structure of claim 1, wherein the first via is in direct contact with a sidewall of the second bonding pad and a sidewall of the third bonding pad facing the sidewall of the second bonding pad.
3. The semiconductor package structure of claim 1, wherein the first via is in direct contact with a top surface of the second bonding pad and a top surface of the third bonding pad.
4. The semiconductor package structure of claim 1, wherein the second bonding pad and the third bonding pad are different portions of a single continuous ring structure.
5. The semiconductor package structure of claim 1, wherein the first semiconductor wafer further includes a fourth bonding pad and the second semiconductor wafer further includes a fifth bonding pad bonded to the fourth bonding pad, and wherein a width of the fourth bonding pad is less than a width of the first bonding pad.
7. The semiconductor package structure of claim 6, wherein a top surface of the second via is coplanar with a top surface of the first via, and a bottom surface of the second via is higher than a bottom surface of the first via.
9. The semiconductor package structure of claim 8, wherein the first semiconductor wafer further includes a fourth bonding pad and the second semiconductor wafer further includes a fifth bonding pad bonded to the fourth bonding pad, and wherein a width of the first bonding pad is greater than a width of the fourth bonding pad.
10. The semiconductor package structure of claim 8, wherein the first via is in direct contact with a top surface of the first bonding pad, a top surface and a sidewall of the second bonding pad, and a top surface and a sidewall of the third bonding pad facing the sidewall of the second bonding pad.
16. The method for preparing a semiconductor package structure of claim 15, wherein a width of the first opening is greater than a width of the second opening.
18. The method for preparing a semiconductor package structure of claim 15, wherein the first opening has a lower portion and an upper portion, the lower portion of the first opening is between the second bonding pad and the third bonding pad, and the upper portion of the first opening exposes a top surface of the second bonding pad and a top surface of the third bonding pad.
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August 31, 2021
January 16, 2024
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