Disclosed is a memory device including a row decoder generating word line (WL) control signals based on a row address from an external device, a first sub-array including memory cells connected to word lines, a first sub-word line driver (SWD) providing a selection voltage or a non-selection voltage to odd-numbered word lines of the word lines based on odd-numbered WL control signals corresponding to the odd-numbered word lines, and a second SWD providing the selection voltage or the non-selection voltage to even-numbered word lines of the word lines based on even-numbered WL control signals corresponding to the even-numbered word lines. The first SWD applies the non-selection voltage to non-selection word lines of the even-numbered word lines, in response to the even-numbered WL control signals, and the second SWD applies the non-selection voltage to non-selection word lines of the odd-numbered word lines, in response to the odd-numbered WL control signals.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The memory device of claim 1, wherein the odd-numbered word lines alternate with the even-numbered word lines in the first sub-array.
7. The memory device of claim 6, wherein the selection transistor includes a vertical channel transistor (VCT).
9. The memory device of claim 8, wherein the first sub-array is between the first sub-word line driver and the second sub-word line driver.
12. The memory device of claim 8, wherein the first and second sub-word line drivers are configured to operate in response to a sub-word line driver enable signal.
18. The memory device of claim 17, wherein the first word line and the third word line are in a first row, and the second word line and the fourth word line are in a second row.
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March 28, 2022
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