A semiconductor memory device includes a plurality of data latch circuits that are used for input and output of data between a sense amplifier circuit and an input/output circuit, and a data bus that is connected to the plurality of data latch circuits. Each of the data latch circuits includes an inverter circuit that temporarily stores data input and output between the sense amplifier circuit and the input/output circuit, and at least three MOS transistors between the inverter circuit and the data bus. The at least three MOS transistors may be multiple N-channel type MOS transistors and at least one P-channel type MOS transistor connected in parallel between the inverter circuit and the data bus, or at least one N-channel type MOS transistor and multiple P-channel type MOS transistors connected in parallel between the inverter circuit and the data bus.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The semiconductor memory device according to claim 1, wherein the at least one P-channel type MOS transistor provided between the data storage unit and the data wiring includes two P-channel type MOS transistors.
3. The semiconductor memory device according to claim 2, wherein one of the at least two N-channel type MOS transistors and one of the two P-channel type MOS transistors form a first complementary transfer gate and another one of the at least two N-channel type MOS transistors and another one of the two P-channel type MOS transistors form a second complementary transfer gate that is connected in series with the first complementary transfer gate between the data storage unit and the data wiring.
5. The semiconductor memory device according to claim 1, wherein the at least two N-channel type MOS transistors provided between the data storage unit and the data wiring include three or more N-channel type MOS transistors.
10. The semiconductor memory device according to claim 1, wherein the vias are aligned in the first direction and extend in a second direction perpendicular to the first direction.
11. The semiconductor memory device according to claim 1, wherein the vias extend in a second direction perpendicular to the first direction and are offset in a third direction perpendicular to the first and second directions.
13. The semiconductor memory device according to claim 12, wherein the at least one N-channel type MOS transistor provided between the data storage unit and the data wiring includes two or more N-channel type MOS transistors.
15. The semiconductor memory device according to claim 14, wherein the at least one P-channel type MOS transistor provided between the data storage unit and the corresponding one of the second data wirings includes two P-channel type MOS transistors.
16. The semiconductor memory device according to claim 15, wherein one of the at least two N-channel type MOS transistors and one of the two P-channel type MOS transistors form a first complementary transfer gate and another one of the at least two N-channel type MOS transistors and another one of the two P-channel type MOS transistors form a second complementary transfer gate that is connected in series with the first complementary transfer gate between the data storage unit and the corresponding one of the second data wirings.
18. The semiconductor memory device according to claim 14, wherein the at least two N-channel type MOS transistors provided between the data storage unit and the corresponding one of the second data wirings include three or more N-channel type MOS transistors.
19. The semiconductor memory device according to claim 14, wherein the at least two N-channel type MOS transistors provided between the data storage unit and the corresponding one of the second data wirings include three or more N-channel type MOS transistors.
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March 2, 2022
February 6, 2024
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