A video processor chip includes a memory circuit, a frame rate converter circuit, and an image compensation circuit. The memory circuit includes first to third storage spaces. The frame rate converter circuit sequentially writes multiple frame data in video data to the first to the third storage spaces respectively, and reads second data in the frame data from the memory circuit to perform a frame rate conversion when first data in the frame data is written to the memory circuit. The second data is a previous frame data of the first data. The image compensation circuit reads third data in the frame data from the memory circuit when the frame rate converter circuit reads the second data, and performs an image compensation according to a difference between the second data and the third data. The third data is a previous frame data of the second data.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The video processor chip of claim 1, wherein the image compensation circuit does not write the plurality of frame data to the memory circuit.
3. The video processor chip of claim 1, wherein the plurality of frame data are a plurality of successive image data.
4. The video processor chip of claim 1, wherein the plurality of frame data sequentially comprise first frame data, second frame data, and third frame data, and the frame rate converter circuit is configured to write the first frame data to the first storage space, write the second frame data to the second storage space, and write the third frame data to the third storage space.
5. The video processor chip of claim 4, wherein the plurality of frame data further comprise fourth frame data, and the frame rate converter circuit is further configured to write to the fourth frame data to the first storage space, in order to overwrite the first frame data.
6. The video processor chip of claim 1, wherein the first data is a next image data that follows the second data.
7. The video processor chip of claim 1, wherein the second data is a next image data that follows the third data.
9. The video processing method of claim 8, wherein the image compensation is performed by an image compensation circuit, and the image compensation circuit does not write the plurality of frame data to the memory circuit.
10. The video processing method of claim 8, wherein the plurality of frame data are a plurality of successive image data.
13. The video processing method of claim 8, wherein the first data is a next image data that follows the second data.
14. The video processing method of claim 8, wherein the second data is a next image data that follows the third data.
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September 29, 2021
February 6, 2024
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