A hybrid semiconductor device includes an interposer substrate, a semiconductor package mounted on the interposer substrate, a molding member on the package substrate covering at least a portion of the semiconductor chip and exposing an upper surface of the semiconductor chip, and a stiffener disposed on an upper surface of the interposer substrate substantially around the semiconductor package.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The hybrid semiconductor device of claim 1, wherein an upper surface of the semiconductor chip is coplanar with an upper surface of the molding member.
3. The hybrid semiconductor device of claim 1, wherein the package substrate includes one of a coreless substrate and a core multilayered substrate.
4. The hybrid semiconductor device of claim 1, wherein the stiffener is a four-walled structure surrounding the semiconductor package and disposed in a peripheral region of the interposer substrate.
5. The hybrid semiconductor device of claim 1, wherein the interposer substrate includes a core multilayer substrate.
6. The hybrid semiconductor device of claim 1, wherein the semiconductor package further includes at least one of a first over passive device mounted on an upper surface of the package substrate and a first under passive device mounted on a lower surface of the package substrate.
7. The hybrid semiconductor device of claim 6, wherein the semiconductor package further includes package connection terminals disposed on the lower surface of the package substrate, and a height of the first under passive device is less than a height of the package connection terminals.
9. The hybrid semiconductor device of claim 8, wherein a pitch between the package connection terminals is less than a pitch between the interposer connection terminals.
10. The hybrid semiconductor device of claim 1, wherein the semiconductor package has a first height relative to an upper surface of the interposer substrate, and the stiffener has a second height relative to the upper surface of the interposer substrate and different from the first height.
12. The hybrid semiconductor device of claim 11, wherein an upper surface of the semiconductor chip is exposed by the molding member.
13. The hybrid semiconductor device of claim 11, wherein the package substrate is one of a coreless substrate and a core multilayered substrate.
14. The hybrid semiconductor device of claim 11, wherein the interposer substrate is a core multilayer substrate.
15. The hybrid semiconductor device of claim 11, wherein the semiconductor package has a first height relative to the upper surface of the interposer substrate, and the stiffener has a second height relative to the upper surface of the interposer substrate different from the first height.
17. The electronic device of claim 16, wherein a pitch between the package connection terminals is less than a pitch between the interposer connection terminals.
18. The electronic device of claim 16, wherein an upper surface of the semiconductor chip is exposed by the molding member.
19. The electronic device of claim 16, wherein the package substrate includes one of a coreless substrate and a core multilayered substrate.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 29, 2021
February 20, 2024
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