Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.
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3. The method of claim 1, further configuring a selected processing unit to transfer data to the second memory bank during the first line access cycle.
5. The method of claim 1, wherein the at least one processing unit comprises a plurality of accelerators configured for pre-defined tasks.
6. The method of claim 5, wherein the plurality of accelerators comprise at least one of a vector multiply accumulate unit or a direct memory access.
7. The method of claim 5, wherein the configuration manager comprises at least one of a RISC processor or a micro-controller.
8. The method of claim 1, further comprising an external interface connected to the plurality of memory banks.
10. The method of claim 9, wherein the words comprise machine instructions.
11. The method of claim 1, wherein the configuration manager comprises a local memory that stores a command to be transmitted to at least one of the plurality of processing units.
12. The method of claim 1, further comprising configuring the memory controller to interrupt the task in response to receiving a request from an external interface.
13. The method of claim 1, wherein the plurality of memory banks includes at least one of DRAM mats, DRAM, banks, flash mats, or SRAM mats.
14. The method of claim 1, wherein the at least one processing unit comprises at least one arithmetic logic unit, at least one vector handling logic unit, at least one register, and at least one direct memory access.
15. The method of claim 1, further comprising configuring the configuration manger and the at least one processing unit to hand over access to the memory controller between each other after finalizing a task.
17. The non-transitory computer-readable medium of claim 16, wherein a selected processing unit is configured to transfer data to the second memory bank during the first line access cycle.
19. The non-transitory computer-readable medium of claim 16, wherein the at least one processing unit comprises a plurality of accelerators configured for pre-defined tasks.
20. The non-transitory computer-readable medium of claim 19, wherein the plurality of accelerators comprise at least one of a vector multiply accumulate unit or a direct memory access.
21. The non-transitory computer-readable medium of claim 19, wherein the configuration manager comprises at least one of a RISC processor or a micro-controller.
22. The non-transitory computer-readable medium of claim 16, further comprising an external interface connected to the plurality of memory banks.
23. The non-transitory computer-readable medium of claim 16, when a number a number of words that can be accessed simultaneously from one of the plurality of memory banks is lower than the number of words that are required simultaneously, divide the number of words required simultaneously between multiple memory banks.
24. The non-transitory computer-readable medium of claim 23, wherein the words comprise machine instructions.
25. The non-transitory computer-readable medium of claim 16, wherein the configuration manager comprises a local memory that stores a command to be transmitted to at least one of the at least one processing unit.
26. The non-transitory computer-readable medium of claim 16, wherein the memory controller is configured to interrupt the task in response to receiving a request from an external interface.
27. The non-transitory computer-readable medium of claim 16, wherein the plurality of memory banks includes at least one of DRAM mats, DRAM, banks, flash mats, or SRAM mats.
28. The non-transitory computer-readable medium of claim 16, wherein the at least one processing unit comprises at least one arithmetic logic unit, at least one vector handling logic unit, at least one register, and at least one direct memory access.
29. The non-transitory computer-readable medium of claim 16, wherein the configuration manger and the at least one processing unit are configured to hand over access to the memory controller between each other after finalizing a task.
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August 9, 2021
February 27, 2024
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