According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The system according to claim 1, wherein when the first command is issued, the third voltage is applied to all the word lines for the first block and the second block.
3. The system according to claim 1, wherein the controller periodically issues the first command.
4. The system according to claim 1, wherein the controller determines a timing of issuance of the first command according to states of the first block and the second blocks.
5. The system according to claim 1, wherein, in response to the first command, the semiconductor memory is configured to Output a busy signal notifying the controller that the semiconductor memory is in a busy state.
6. The system according to claim 5, wherein, after the data is read from the first block or the second block, the semiconductor memory is configured to output a ready signal notifying the controller that the semiconductor memory is in a ready state.
7. The system according to claim 1, wherein the driver circuit is configured to apply the third voltage to all the word lines included in the first block during the first period via the first row decoder.
10. The system according to claim 9, wherein when the first voltage and the second voltage are applied to the first word lines, a potential of the first block selection signal is set to a fourth voltage larger than the second voltage.
11. The system according to claim 9, wherein upon the negation of the first block selection signal, the first word lines are set in an electrically floating state.
12. The system according to claim 9, wherein, when the first command is issued to the semiconductor memory, the first block decoder is configured to assert the first block selection signal and the second block decoder is configured to assert the second block selection signal.
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December 20, 2021
February 27, 2024
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