A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The method for manufacturing the semiconductor device according to claim 1, wherein the interconnection layer comprises a solder bonding structure, a metal-to-metal direct bonding structure, or a hybrid bonding structure.
3. The method for manufacturing the semiconductor device according to claim 1, wherein the protective layer is a dielectric layer.
5. The method for manufacturing the semiconductor device according to claim 4, wherein the etching process is a wet etching process.
6. The method for manufacturing the semiconductor device according to claim 1, wherein a top edge of the sidewall layer is higher than an exposed surface of the first component layer.
7. The method for manufacturing the semiconductor device according to claim 6, wherein the photoresist layer covers the exposed surface and the top edge of the sidewall layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 17, 2021
March 5, 2024
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.