A semiconductor package including a first package substrate, a first semiconductor chip on a top surface of the first package substrate, an interposer electrically connected to the first package substrate on a top surface of the first semiconductor chip, and a molding layer configured to cover the first package substrate and the first semiconductor chip may be provided. The interposer may include an interposer trench recessed from a bottom surface of the interposer that faces both the top surface of the first semiconductor chip and the top surface of the first package substrate, and an interposer hole penetrating the interposer. The molding layer may include a filling portion filling a region between the first package substrate and the interposer, a through portion filling the interposer hole, and a cover portion covering at least a part of a top surface of the interposer.
Legal claims defining the scope of protection, as filed with the USPTO.
4. The semiconductor package of claim 1, wherein the interposer trench is arranged in plural number along a first direction parallel to the bottom surface of the interposer.
5. The semiconductor package of claim 4, wherein the interposer trench arranged in plural number is parallel to the top surface of the first package substrate and extends along a second direction crossing the first direction.
6. The semiconductor package of claim 1, wherein the filling portion, the through portion, and the cover portion are portions of an integral body.
7. The semiconductor package of claim 1, wherein the interposer includes a lower pad exposed from the bottom surface of the interposer, an upper pad exposed from the top surface of the interposer, and a through via penetrating the interposer to connect the lower pad to the upper pad.
10. The semiconductor package of claim 1, wherein the molding layer includes an epoxy molding compound (EMC).
12. The semiconductor package of claim 11, wherein the interposer trench extends in a first direction parallel to the surface of the package substrate.
13. The semiconductor package of claim 12, wherein a width of the interposer hole is smaller than a width of the interposer trench in a second direction that is parallel to the top surface of the package substrate and crosses the first direction.
14. The semiconductor package of claim 11, wherein at least a part of the interposer trench overlaps an edge of the semiconductor chip in plan view.
16. The semiconductor package of claim 15, wherein a part of the molding layer covers at least a part of a top surface of the interposer.
18. The semiconductor package of claim 17, wherein a part of the molding layer covers at least a part of a top surface of the interposer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 22, 2021
March 5, 2024
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