Techniques for debugging a circuit including a global counter configured to continuously increment, a comparator configured to transmit a clock stop signal based on a comparison of a comparator value and a counter value of the global counter, and clock stop circuitry configured to receive the clock stop signal and stop a clock signal to one or more portions of the electronic device.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The electronic device of claim 1, wherein the comparator value is based on a modified value of the counter value at the first point in time.
3. The electronic device of claim 2, wherein the counter value at the first point in time is increased or decreased to determine the comparator value.
4. The electronic device of claim 2, wherein the counter value at the first point in time is modified by a debug host.
5. The electronic device of claim 1, wherein the selection is associated with a combination of events.
6. The electronic device of claim 1, further comprising a comparator register configured to store the comparator value.
7. The electronic device of claim 1, wherein the counter value is continuously incremented based on a clock of the electronic device.
10. The method of claim 9, wherein the comparator value is based on a modified value of the counter value at the first point in time.
11. The method of claim 10, wherein the counter value at the first point in time is increased or decreased to determine the comparator value.
12. The method of claim 10, wherein the counter value at the first point in time is modified by a debug host.
13. The method of claim 9, further comprising receiving the comparator value.
14. The method of claim 9, wherein the counter value is continuously incremented based on a clock of the electronic device.
15. The method of claim 9, wherein the incrementing of the counter value by the global counter begins at power on of a circuit device that includes the global counter and continues while power is applied to the circuit device.
17. The circuit of claim 16, wherein the comparator value is based on a modified value of the counter value at the first point in time.
18. The circuit of claim 17, wherein the counter value at the first point in time is increased or decreased to determine the comparator value.
19. The circuit of claim 17, wherein the counter value at the first point in time is modified by a debug host.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 27, 2021
March 12, 2024
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