A semiconductor package includes a substrate, a package structure, and a lid structure. The package structure is disposed on the substrate. The lid structure is disposed over substrate, wherein the lid structure includes a main body covering and surrounding the package structure and a plurality of rib portions protruded from the main body and extended toward the package structure.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The semiconductor package as claimed in claim 1, wherein the lid structure is integrally formed.
3. The semiconductor package as claimed in claim 1, wherein the plurality of rib portions are extended horizontally toward the package structure.
4. The semiconductor package as claimed in claim 1, wherein the plurality of rib portions extended vertically toward the substrate.
5. The semiconductor package as claimed in claim 1, wherein the main body further comprising a cover portion covering the package structure and a ring portion disposed over substrate and surrounding the package structure.
6. The semiconductor package as claimed in claim 5, wherein the cover portion comprises a package region aligned with the package structure and a peripheral portion surrounding the package region and connected to the ring portion, and a thickness of the package region is greater than a thickness of the peripheral portion.
7. The semiconductor package as claimed in claim 1, wherein each of the plurality of rib portions comprises a chamfer facing the package structure and the substrate.
8. The semiconductor package as claimed in claim 1, wherein the package structure comprises a plurality of device dies and a filling material filling a gap between adjacent two of the plurality of device dies.
10. The semiconductor package as claimed in claim 9, wherein the plurality of rib portions are protruded from the ring portion and extended horizontally toward the package structure.
11. The semiconductor package as claimed in claim 9, wherein the plurality of rib portions are protruded from the cover portion and extended vertically toward the substrate.
12. The semiconductor package as claimed in claim 9, wherein the cover portion comprises a package region aligned with the package structure and a peripheral portion surrounding the package region and connected to the ring portion, and a thickness of the package region is greater than a thickness of the peripheral portion.
13. The semiconductor package as claimed in claim 9, wherein the lid structure is integrally formed.
14. The semiconductor package as claimed in claim 9, wherein the lid structure further comprises a plurality of fastening components extending through the cover portion for fastening the cover portion to the ring portion.
15. The semiconductor package as claimed in claim 9, wherein the cover portion comprises a plurality of cover engaging parts, and the ring portion comprises a plurality of ring engaging parts engaged with the plurality of cover engaging parts respectively.
16. The semiconductor package as claimed in claim 9, wherein a thermal conductivity of the cover portion is greater than a thermal conductivity of the ring portion.
18. The semiconductor package as claimed in claim 17, wherein the lid structure further comprises a cover portion attached to the upper surface of the package structure and a ring portion attached to substrate and surrounding the package structure.
19. The semiconductor package as claimed in claim 18, wherein the plurality of rib portions disposed on the ring portion and extended horizontally toward the package structure.
20. The semiconductor package as claimed in claim 18, wherein the plurality of rib portions disposed on the cover portion and extended vertically toward the substrate.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 19, 2021
March 12, 2024
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