A first processing unit such as a graphics processing unit (GPU) pipelines that execute commands and a scheduler to schedule one or more first commands for execution by one or more of the pipelines. The one or more first commands are received from a user mode driver in a second processing unit such as a central processing unit (CPU). The scheduler schedules one or more second commands for execution in response to completing execution of the one or more first commands and without notifying the second processing unit. In some cases, the first processing unit includes a direct memory access (DMA) engine that writes blocks of information from the first processing unit to a memory. The one or more second commands program the DMA engine to write a block of information including results generated by executing the one or more first commands.
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2. The method of claim 1, wherein the one or more user mode operations are performed by the GPU responsive to completing execution of the first command.
3. The method of claim 1, wherein the one or more user mode operations are performed without notifying the second processing unit.
4. The method of claim 1, wherein selecting the one or more additional commands includes generating at least one additional command of the one or more additional commands for execution by the GPU.
5. The method of claim 1, wherein selecting the one or more additional commands includes identifying at least one additional command for execution by the GPU.
6. The method of claim 5, wherein receiving the first command for execution includes receiving state information associated with the first command from the second processing unit, and wherein identifying the at least one additional command includes identifying the at least one additional command based on the state information.
7. The method of claim 1, wherein at least one of the one or more additional commands causes the GPU to write to memory one or more blocks of information comprising results generated from executing the first command.
8. The method of claim 1, wherein the one or more additional commands include at least one of a filtering operation, a shader that is launched by the GPU, or a modification to a number of frames per second.
10. The GPU of claim 9, wherein the one or more user mode operations are performed responsive to completing execution of the first command.
11. The GPU of claim 9, wherein the one or more user mode operations are performed without notifying the second processing unit.
12. The GPU of claim 9, wherein the selection of the one or more additional commands includes generation of at least one additional command of the one or more additional commands.
13. The GPU of claim 9, wherein the selection of the one or more additional commands includes identifying at least one additional command for execution by the GPU.
14. The GPU of claim 13, wherein the first command is associated with state information received from the second processing unit, and wherein identifying the at least one additional command includes identifying the at least one additional command based on the associated state information.
15. The GPU of claim 9, wherein at least one of the one or more additional commands causes a direct memory access (DMA) engine of the GPU to write to memory one or more blocks of information comprising results generated from executing the first command.
16. The GPU of claim 9, wherein the one or more additional commands include at least one of a filtering operation, a shader that is launched by the GPU, or a modification to a number of frames per second.
18. The method of claim 17, wherein selecting the at least one second command includes generating the at least one second command.
19. The method of claim 17, wherein selecting the at least one second command includes identifying the at least one second command based on state information associated with the at least one first command.
20. The method of claim 17, wherein the at least one second command includes one or more of a filtering operation, a shader initiated by the GPU, or a modification to a number of frames per second.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 16, 2022
March 19, 2024
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