A system may include a field programmable gate array (FPGA) based gateway comprising: a network interface configured to receive data packets containing proposed transactions, and validation logic circuitry configured to validate one or more headers or application-layer of the data packets in accordance with filter rules. The system may also include an FPGA based router comprising: a network interface configured to receive the data packets from the gateway, and parsing and lookup circuitry configured to compare the header field or application-layer field values in the data packets to those in a forwarding table. The system may also include an FPGA based matching engine comprising: a network interface configured to receive the data packets from the router, transaction validation circuitry configured to validate the proposed transactions based on information from state memory and policies, and matching algorithm circuitry configured to match pair of proposed transactions according to pre-determined criteria.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The FPGA based matching engine of claim 1, wherein the state memory contains information related to previously fulfilled transactions involving transaction subjects or source identifiers in common with those of at least some of the data packets, and wherein the source identifiers specify entities originating the proposed transactions.
3. The FPGA based matching engine of claim 1, wherein the policies to be applied to the proposed transactions are formulated as rules, and wherein the rules specify limits to total amounts of certain transaction subjects that can be fulfilled within a predetermined period of time.
4. The FPGA based matching engine of claim 1, wherein the policies to be applied to the proposed transactions are formulated as rules, and wherein the rules specify limits to total amounts of certain transaction subjects per particular instances of source identifiers that can be fulfilled within a predetermined period of time.
6. The FPGA based matching engine of claim 1, wherein parts of the FPGA based matching engine support virtualization into slices, wherein the pending transaction memory stores proposed transactions that were validated with their associated slices, and wherein the matching algorithm circuitry is further configured to only match pairs of pending transactions with a common associated slice.
9. The FPGA based matching engine of claim 1, wherein the FPGA based matching engine is also configured to transmit receipt confirmations for the proposed transactions that were validated but have not yet been matched.
10. The FPGA based matching engine of claim 1, wherein the FPGA based matching engine is also configured to transmit fulfilment confirmations for the proposed transactions that were matched.
12. The method of claim 11, wherein the state memory contains information related to previously fulfilled transactions involving transaction subjects or source identifiers in common with those of at least some of the data packets, and wherein the source identifiers specify entities originating the proposed transactions.
13. The method of claim 11, wherein the policies to be applied to the proposed transactions are formulated as rules, and wherein the rules specify limits to total amounts of certain transaction subjects that can be fulfilled within a predetermined period of time.
14. The method of claim 11, wherein the policies to be applied to the proposed transactions are formulated as rules, and wherein the rules specify limits to total amounts of certain transaction subjects per particular instances of source identifiers that can be fulfilled within a predetermined period of time.
15. The method of claim 11, wherein the FPGA based matching engine also contains log memory, and wherein the transaction validation circuitry is configured to write information from the data packets that fail validation into the log memory.
16. The method of claim 11, wherein parts of the FPGA based matching engine support virtualization into slices, wherein the pending transaction memory stores proposed transactions that were validated with their associated slices, and wherein the matching algorithm circuitry is further configured to only match pairs of pending transactions with a common associated slice.
17. The method of claim 16, wherein the FPGA based matching engine also contains lookup table memory configured with mappings of the transaction subjects to the slices or with combinations of transaction subjects and source identifiers to the slices, wherein source identifiers specify entities originating the proposed transactions.
18. The method of claim 17, wherein the FPGA based matching engine also contains lookup circuitry configured to retrieve indications of the slices associated with data packets from the lookup table memory and provide the indications of the slices retrieved to the pending transaction memory or the matching algorithm circuitry.
19. The method of claim 11, wherein the FPGA based matching engine is also configured to transmit receipt confirmations for the proposed transactions that were validated but have not yet been matched.
20. The method of claim 11, wherein the FPGA based matching engine is also configured to transmit fulfilment confirmations for the proposed transactions that were matched.
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June 8, 2021
March 19, 2024
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