Patentable/Patents/US-11935959
US-11935959

Semiconductor device comprising oxide semiconductor film comprising nanocrystal

PublishedMarch 19, 2024
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A change in electrical characteristics of a semiconductor device including an interlayer insulating film over a transistor including an oxide semiconductor as a semiconductor film is suppressed. The structure includes a first insulating film which includes a void portion in a step region formed by a source electrode and a drain electrode over the semiconductor film and contains silicon oxide as a component, and a second insulating film containing silicon nitride, which is provided in contact with the first insulating film to cover the void portion in the first insulating film. The structure can prevent the void portion generated in the first insulating film from expanding outward.

Patent Claims
1 claims

Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.

Claim 4

Original Legal Text

4. The semiconductor device according to claim 3, wherein the low-density region has a size in the order of several nanometers.

Plain English Translation

A semiconductor device includes a substrate with a high-density region and a low-density region of semiconductor material. The low-density region is formed by removing portions of the semiconductor material, creating a porous structure. This porous structure has a size in the order of several nanometers, which enhances the device's performance by improving charge carrier mobility or reducing parasitic capacitance. The high-density region remains intact, providing structural support and electrical connectivity. The porous low-density region can be used in transistors, memory cells, or sensors to optimize electrical properties. The nanometer-scale dimensions of the low-density region enable precise control over device characteristics, such as threshold voltage or leakage current, while maintaining mechanical stability. The device may also include insulating layers or conductive contacts to integrate the porous structure into larger circuits. This design addresses challenges in semiconductor miniaturization, such as maintaining performance at advanced technology nodes while reducing power consumption and improving reliability.

Classification Codes (CPC)

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Patent Metadata

Filing Date

October 12, 2022

Publication Date

March 19, 2024

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